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Altera_Forum
Honored Contributor
14 years agoThe BAR is by itself, if I understand the question properly. There are other registers that access the other modules. Those all work fine. This one is a point in the contiguous memory map that has been identified. For example, this register sits at 0x28000 and another module consumes 0x27000 - 0x27FFF in memory space.
I assume that the OS, drivers, and the PCIe handles the BAR offsetting automatically. I did not write the OS drivers (Linux), but can forward questions to the team. With respect to the Avalon bridge diagnostic work you are speaking of, I am familiar with FPGA's and Altera devices from several years ago. I have not familiarized myself with the JTAG and Avalon-MM Bridge. I can give it a go and see what I find. Thanks for the help.