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I need to implement ROM with 12 bytes of information in the FPGA that is memory mapped and accessible through the PCIe bus.
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Is this memory accessible in a PCIe BAR by itself, or with other registers?
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The address is specified in the location the off chip processor is expecting.
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What address? There's a Qsys address, and there is an offset-into-the-PCIe-BAR address?
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The external processor is then programmed to read the addresses for the information contained.
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The external processor would first need to read the BAR address, then map that into its memory map. The granularity of the BAR size is 256-bytes, however, OSes like Linux will only map 4kB pages, so you then need to determine the offset into the BAR to find where your registers actually start.
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What might be going on here?
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I suspect that you are accessing the registers at an alias address where the incomplete decoding of the Qsys fabric is allowing you to access some, but not all the registers at the alias address.
Add a Avalon-MM BFM to your Qsys system, and perform read/write accesses on the memory. That'll convince you the memory works correctly. Then use a PCIe BFM to perform PCIe transactions to the same memory.
If you don't have a simulation setup, then try using SignalTap II to probe the Avalon-MM master address that comes out of the PCIe-to-Qsys bridge. Check that those addresses are what you expect. You could also add a JTAG-to-Avalon-MM bridge to access your on-chip RAM directly, and that'll also help convince you the problem is PCIe related.
Cheers,
Dave
Honored Contributor
