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New ContributorOn-chip Debugging Design Examples .qar can't be loaded
Hi Horia,
Can you navigate to below link and download Introduction to FPGA Simulation and Debug materials there?
https://software.intel.com/content/www/us/en/develop/topics/fpga-academic/materials-workshops.html
Design file you referred probably an old design I can see 10.1 release.
Super ContributorHi Horia,
Can you navigate to below link and download Introduction to FPGA Simulation and Debug materials there?
https://software.intel.com/content/www/us/en/develop/topics/fpga-academic/materials-workshops.html
Design file you referred probably an old design I can see 10.1 release.
New ContributorGreat resources, I managed to optimize the design, achieving 159 SPS with 8 channels on and 1.2k SPS with 1 channel on - which should be sufficient. I'm still printing to the Nios2 terminal - the limiting factors were due to timing and there are more optimizations possible.
On a side note, I scripted a TCL adapter for reading the memory directly, but printing to JTAG UART still performs better.
