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Altera_Forum
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8 years ago

Odd behavior with matching-case (vhdl 2008)

Hello! I'm trying to use the matching-case syntax introduced in vhdl 2008 but I'm having a bit of a problem. Take the following piece of code, say a register map for example: clk : in ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

I would raise this as a synth bug to altera, as you will now have a simulation/synthesis missmatch.

Any chance you have a Prime pro license? Prime pro is meant to have full vhdl 2008 support, so I assume a different compile engine.