Not operational Clock Skew

Hi everybody,

I've implemented a design which has different input ports included for being able to configure different options of the block, this ports are fed by different constants blocks (lpm_constant) which I edit with 'In-system memory editor' to test different configurations with Signal Tap. My problem is related to timing analyzing since Classic T.A. tells me: "Not operational Clock Skew > Data Delay" in the 'Clock hold section'. Every error belongs to one of these constants. I have tried to solve it by means of Assignment editor though I have not been able to fix it. Any idea?

Thanx

J.