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Altera_Forum's avatar
Altera_Forum
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10 years ago

not able to see the output on the oscilloscope

Hello everyone, I have programmed my FPGA De0 nano board to generate short pulse of 1000 ps and the time between the next pulse is 10 us. I want to see this pulse on digital oscilloscope. I hav...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

DE0-Nano is with CIV E device. As Alex said, the max PLL output frequency for CIV E device is 472.5MHz only. Even if you are using LVDS, the max data rate is 840Mbps only.