Forum Discussion
Altera_Forum
Honored Contributor
10 years agohi,
if i use your vhdl file i would write this in the top level entity: nco_inst : nco13 port map( clk => clk_in, reset_n => reset_n ... ); and one more thing i noticed in the first vhdl file you sent : look at reset_n and clk_en, they got the same signal "clk_en". I doubt that reset_n has the same polarity than clk_en.