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Looks like, full_adder hasn't been set as the project's design top and was actually
not compiled. You can check the actual project structure in the hierarchy view.
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Thanks, that turned out to be my problem in the end. I was unaware that you needed to set it as the top level entity. As in regards to the earlier post, what do you mean by post my project. Is there a way to post files in these forums? The actual project is to design a stopwatch that outputs to a seven segment display that will output to an fpga board, using dff's to form a register, the adder circuit, a frequency divider, and several other parts. I dont know if that would be too large.
As of now i'm almost done however when i compile i keep getting two warnings, Firstly that "Warning: Output pins are stuck at VCC or GND", and also that "Warning: Design contains 3 input pin(s) that do not drive logic". Then when i try to simulate my design those outputs are non responsive. Are there any general causes for these warnings i could look at or are they fairly specific.
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