No paths found for timing analysis

An obvious issue in this post is that the problem should not be about chasing timing paths but about design itself:

Firstly, the computation of multiply,add,divide,subtract and modulus requires careful breakdown of these processes into several pipe stages.

Secondly, there is no clock and no clock edge process. The attempt to do that in the following code:

if read_write = '0' then

read_write <= '1';

end if;

if read_write = '1' then

read_write <= '0';

end if;

produces an oscillatory signal that can't be useful in FPGAs

The term register in FPGAs is used to mean clocked flipflop. The term latch is used to mean a flipflop without clock-unlike academic definition of register.