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Timing tools usually check paths between two registers. In your design I can't see any registers.
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This is not exactly true. When you use a process in VHDL design, the synthesizer implements registers for all signals to which an assignment is performed. In other words, an assignment in process is not instant and every signal has a buffer (this differs a signal from a variable).
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I can't confirm the observation.
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Consider the following example:
entity (<the same as in the previous example>)
ARCHITECTURE a OF Component_test_wo_library IS
SIGNAL Read_Write : STD_LOGIC := '0';
BEGIN
Component_test_wo_library:
PROCESS (Input1_I,Input2_I,Input3_I,Input4_I,Input5_I,Inpu t6_I,Read_Write) IS
BEGIN
Read:
IF (Read_Write = '0')
THEN
Read_Write <= '1';
END IF;
Result:
IF (Read_Write = '1')
THEN
Read_Write <= '0';
Result_O <= std_logic_vector( (("0" & unsigned(Input1_I) * unsigned(Input2_I)) + (unsigned(Input4_I) mod unsigned(Input5_I))) /
--NO SUBTRACTION OPERATION
unsigned(Input6_I));
END IF;
END PROCESS;
END a;
This example compiles without a warning and I get the following worst-case tpd - 63,104ns. However, as soon as I add subtraction, the tool cannot provide me with this info because it thinks that the output is not connected to the inputs.
Therefore, the subtraction operation somehow affects the paths and timing analysis, although RTL viewer shows that everything is connected.
Honored Contributor
