Forum Discussion
FCive
Occasional Contributor
Occasional ContributorNo hardware detected in beta bus analyzer
Dear community, I have a Terasic DE5-Net FPGA based on Stratix V FPGA. I would like to monitor the Avalon MM bus by mean of the Bus analyzer toolkit. I followed the guide of this link (https://fpgaw...
sstrell
Super Contributor
Super ContributorI have not tried this with a hierarchical system design, so I'm not sure if that is the problem.
As for the warning, the monitor is most likely on the master side (single monitor monitors all transactions to/from that master), so there's no reason/need to add these extra monitors.
