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FCive's avatar
FCive
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

No hardware detected in beta bus analyzer

Dear community, I have a Terasic DE5-Net FPGA based on Stratix V FPGA. I would like to monitor the Avalon MM bus by mean of the Bus analyzer toolkit. I followed the guide of this link (https://fpgaw...
FCive's avatar
FCive
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

I have noticed that, after HDL generation in the platform designer, the report gives me the following warning for all the slaves that I considered:

Warning: Cannot insert performance monitor for sysid_qsys_0.control_slave because it only has one connection. Add more connections to allow monitor insertion.

In the Instrumentation tab, I have added one master MM and many slaves MM connect to the same master MM. While the master monitor seems to be ok, I have the above warning for all the slaves.

What am I missing? Do you have any idea?

Thank you.

Federico