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FCive's avatar
FCive
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

No hardware detected in beta bus analyzer

Dear community, I have a Terasic DE5-Net FPGA based on Stratix V FPGA. I would like to monitor the Avalon MM bus by mean of the Bus analyzer toolkit. I followed the guide of this link (https://fpgaw...
FCive's avatar
FCive
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

I did not write that I would like to monitor the avalon bus of a qsys subsystem. Thus, the signals that I would like to monitor are present in the subsystem interconnect requirements tab but they are not present in the interconnect requirements tab of the top instance of qsys hierarchy. Could this be the problem?

Thank you.

Federico