Forum Discussion
FCive
Occasional Contributor
Occasional ContributorNo hardware detected in beta bus analyzer
Dear community, I have a Terasic DE5-Net FPGA based on Stratix V FPGA. I would like to monitor the Avalon MM bus by mean of the Bus analyzer toolkit. I followed the guide of this link (https://fpgaw...
FCiveOccasional Contributor
Occasional ContributorI did not write that I would like to monitor the avalon bus of a qsys subsystem. Thus, the signals that I would like to monitor are present in the subsystem interconnect requirements tab but they are not present in the interconnect requirements tab of the top instance of qsys hierarchy. Could this be the problem?
Thank you.
Federico
