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FCive's avatar
FCive
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

No hardware detected in beta bus analyzer

Dear community, I have a Terasic DE5-Net FPGA based on Stratix V FPGA. I would like to monitor the Avalon MM bus by mean of the Bus analyzer toolkit. I followed the guide of this link (https://fpgaw...
FCive's avatar
FCive
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

I use the 18.1 version of Quartus and, as described in the guide, from version 14.1 "JTAG Debug Link is auto-instantiated and is not a selectable IP core from the IP Catalog".

Thus, I did not add anything in the design and I only enabled the instrumentation.

​Do I have to add something else in the design?

Thank you.

​

Federico