Forum Discussion
Altera_Forum
Honored Contributor
10 years agoNo feasible entries for subprogram read
I don't understand: I have used this piece of code over and over again, it has always worked. Instead, now I can't get rid of the error No feasible entries for subprogram "read". Any idea would b...
Altera_Forum
Honored Contributor
10 years agodid you include the std_logic_textio library, or use VHDL 2008 compile options?
I assume this is simulation code, because this code cannot be synthesised.