Forum Discussion
Altera_Forum
Honored Contributor
9 years agodid you include the std_logic_textio library, or use VHDL 2008 compile options?
I assume this is simulation code, because this code cannot be synthesised.did you include the std_logic_textio library, or use VHDL 2008 compile options?
I assume this is simulation code, because this code cannot be synthesised.