I have created a Qsys circuit using Nios II/e, with a clock frequency of 50 MHz. Other peripherals are also connected, as shown in the attached photo. I wrote a program in Eclipse, and when I checked the real-time toggling of the GPIO pin, I found the ON time to be 85 microseconds and the OFF time to be 86 microseconds. However, I specified an ON time and OFF time of 1 microsecond each in the program. Could you kindly help me understand why there is such a significant difference?

What are you using as your reference clock source? Just because you specify a 50 MHz clock in Quartus doesn't mean it will work correctly unless you actually apply a 50 MHz clock. Where are you specifying the time? Do you mean your timing constraints (.sdc)? More detail needed.

In the Platform Designer (.qsys file), I have specified the clock source (50 MHz). I have attached a screenshot of it.

Hi,the question is, which clock source is actually connected to qsys exported clk input port.And also, how do you generate intended 1 us timing in your code?

I am working on generating a precise 1 µs timing. Here are the steps I followed:Here are the steps I followed:Made the connections: Nios II/e processor with the clock and other desired components(See attached picture).Compiled the project.Configured the Pin Planner.Recompiled the project.Uploaded the .sof file to the FPGA using the Programmer tool.Used the .sopcinfo file to write code in Eclipse.However, when I run the code and check the toggling of the GPIO pins, I am not getting the desired output. I specified a 1 µs toggling of the pin in the program, but I am observing 85 µs instead.Can you help me resolve this issue?

That's great but you still haven't explained how you are providing the 50MHz clock to the design in hardware or the code that you are using to help understand why this might be a software issue instead of a hardware issue. Just saying in Platform Designer "I'm using a 50 MHz clock" doesn't make it happen unless you are actually providing that in hardware.

NIOS ii/e clock frequency differ from real-time running frequency.

20 Replies

tehjingy_Altera
Regular Contributor
11 months ago
Hi

From the pin planner screenshot, could you try changing the IO standard for the clock pin to 3.3V instead of 2.5V?
Another question is could you try increasing the delay to 10us if the delay is proportional or not?

Regards
Jingyang, Teh
- Asifa
  New Contributor
  11 months ago
  It's still the same with 3.3V to clock pin. If we set the delay to 1 µs, it shows 79 µs. When we increase the delay to 10 µs, it shows 89 µs.
tehjingy_Altera
Regular Contributor
11 months ago
Hi

Could you check the ALT_CPU_FREQ define in the system.h file? This file should be in the output folder.
The value should be 50Mhz, the value is used to calculate the delay in the usleep function.

Regards
Jingyang, Teh
tehjingy_Altera
Regular Contributor
11 months ago
Hi

Do you have any update on this case?
Did you managed to check the define of the clock in the system.h ?

Regards
Jingyang, Teh
tehjingy_Altera
Regular Contributor
10 months ago
Hi

As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Regards
Jingyang, Teh

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NIOS ii/e clock frequency differ from real-time running frequency.

20 Replies

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