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Honored Contributor
Honored ContributorNios II read/write to DDR3 using external DDR3 controller
Hello, I have a simple Qsys SoC consisting of Nios II, on-chip memory, 2 Avalon MM masters and 1 AXI slave. I have connected the Nios II to each Avalon MM master (one for read and one for...
Altera_ForumHonored Contributor
Honored ContributorThis looks correct and the addressing should be the address you put on the master agents. The address would get passed through to the AXI interface but only the offset. In other words, when you perform a read, you access 0x2xxx_xxxx to access the read master agent, but the address passed to the AXI interface would be the offset. So 0x2000_0000 would do a read at DDR memory address location 0x0000_0000. I don't know if this helps.
