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1. Latches are bad because they are basically asynchronous circuits and prone to glitches, timing is affected by process, voltage, temperature and you cannot analyse them in timing analysis. In an FPGA they have to be built from luts so you're not using the registers that are provided to provide clean timed designs.
In your case - why not synchronise the whole lot to a system clock (not a logic generated clock) with clock enables if you need them.
2. It makes no sense. This is not software - circuits cannot have actions occur in some given order based on some language. For any output, there must be an input. Think about the circuit you are writing for - not the code you are writing. It is a hardware description language (not a programming language) afterall.
If it makes more sense - an FPGA can be used to build a microprocessor - it is not a microprocessor iteself.
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Could you make me clear what you mean in "why not synchronise the whole lot to a system clock (not a logic generated clock) with clock enables if you need them."?
I am not getting it.
Honored Contributor
