Newbie vs VHDL: season 01 episode 01

newbie vs vhdl: season 01 episode 02

Hi all

I have a few more question:

1. I read that it is good practice to avoid latches but I cannot understand why they are so bad, in particular I had designed a state machine for a counter: on state A it counts and update a signal, let's call this signal internal_counter, on state B it gives internal_counter as an input to the output value output_counter <= internal_counter.

In this way I had latches for all the elements of the std_logic_vector called internal_counter but if I try to reset those value for instance wiriting

when stop =>
output_counter <= internal counter;
internal_counter <= X"000";
next_state <= start;

this proves to be a concurrent statement and so the output is just zeros and so not working. I would like to avoid a third state as long as I do not want to miss any rising edge of the clock controlling the switching between states and I would like to output just a single value at the end of the counting operations. So a concurrent statement out of the process it is likely to avoid any kind of latches and reset issues but give several outputs, not just a single value.

when stop =>
internal_counter <= X"000";
next_state <= start;
end process;
output_counter <= internal_counter;

2. How do you implement sequential statements working on the same signal and does it make sense? It would mean using an FPGA like a microprocessor...