--- Quote Start ---
1) If your design only requires a single process, then sure, but there's no reason not to have multiple processes. Different signals can be written to in different processes based on different circumstances, but you do have to watch out for multiple drivers on a signal. The Quartus compiler will flag any errors like this making it easy to fix them.
2) There's no reason I can think of to not just create the 24-bit counter. Is your concern functionality, timing, resources..?
3) No difference though you only need x"000" for the second one.
4) STD_LOGIC_1164 and NUMERIC_STD are the libraries you should be using for all designs and they make it much easier to design with.
--- Quote End ---
--- Quote Start ---
1. Use whatever is most readable for someone who has never seen your code before.
2. Id just go with the 24 bit counter. Quartus knows what you want and will be more readable for someone whos never read your code before after you've left the company.
3. They are both the same. Think about the poor intern who has to read your code when you're out sick.
4. Yes and no. Use appropriate types for the situation. Unsigned/signed for arithmetic. Integers if life is easier. Booleans sometimes for quick code:
signal something_happened : boolean;
something_happened <= (ip = '1');
....
if something_happened then
--react
end if;
Think about your replacement when you've been promoted and you dont want your workers to laugh at your terrible code.
--- Quote End ---
Ok thank you both now it's everything clear, I would go for the 24-bit, I was more familiar with this kind of split structure for previous designs I have studied/designed -- of course they were not on FPGAs
I should offer you a pint for the advices
Stay tuned for episode 2 :lol:
Honored Contributor
