--- Quote Start ---
I think you've come across a bug...
Quartus should do it automatically for you. There's a synthesis setting for that and it's set to 70.
A work arround is to use an LCELL primitive to break it, like this:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE IEEE.numeric_std.ALL;
entity rc_adder is
generic (
nblocks: integer := 40
);
Port ( clk : in STD_LOGIC;
a_in : in STD_LOGIC;
b_in : in STD_LOGIC;
r : out STD_LOGIC;
load : in STD_LOGIC);
end rc_adder;
architecture Behavioral of rc_adder is
component lcell
port (
a_in : in std_logic;
a_out : out std_logic);
end component;
constant vsize : integer := nblocks * 32;
signal a, b : STD_LOGIC_VECTOR(vsize-1 downto 0);
signal rout : STD_LOGIC_VECTOR(vsize-1 downto 0);
signal sum : std_logic_vector(vsize - 1 downto 0);
signal carry_a : std_logic_vector(nblocks downto 0);
signal carry_b : std_logic_vector(nblocks downto 0);
begin
carry_b(0) <= '0';
adders : for i in 1 to nblocks generate
adder : entity work.adder_32
port map(
carry_in => carry_b(i-1),
a => a(32*i-1 downto 32*(i-1)),
b => b(32*i-1 downto 32*(i-1)),
z => sum(32*i-1 downto 32*(i-1)),
carry_out => carry_a(i)
);
lc : lcell
port map (
a_in => carry_a(i),
a_out => carry_b(i)
);
end generate;
add : process
begin
wait until clk'event and clk = '1';
if (load = '1') then
a <= a(vsize-2 downto 0) & a_in;
b <= b(vsize-2 downto 0) & b_in;
rout <= rout(vsize-2 downto 0) & '0';
r <= rout(vsize-1);
else
rout <= sum;
end if;
end process add;
end Behavioral;
--- Quote End ---
thank you very much rbugalho! im quite new to vhdl and im not quite understand the part you write, can you please expain it a bit?
Honored Contributor
