Newbie question about long control signal

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

USE IEEE.numeric_std.ALL;

entity rc_adder is

generic (

vsize: integer := 440

);

Port ( clk : in STD_LOGIC;

a_in : in STD_LOGIC;

b_in : in STD_LOGIC;

r : out STD_LOGIC;

load : in STD_LOGIC);

end rc_adder;

architecture Behavioral of rc_adder is

signal a, b : STD_LOGIC_VECTOR(vsize-1 downto 0);

signal rout : STD_LOGIC_VECTOR(vsize-1 downto 0);

begin

add : process

begin

wait until clk'event and clk = '1';

if (load = '1') then

a <= a(vsize-2 downto 0) & a_in;

b <= b(vsize-2 downto 0) & b_in;

rout <= rout(vsize-2 downto 0) & '0';

r <= rout(vsize-1);

else

rout <= std_logic_vector(signed(a) + signed(b));

end if;

end process add;

end Behavioral;