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Altera_Forum
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16 years ago

New to VHDL. Help with errors

Can you tell me why im getting these errors for this code: LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; ENTITY DAC2 IS PORT( hardwarecontrol: IN STD_LOG...
Altera_Forum's avatar
Altera_Forum
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16 years ago

In my opinion, the bit selection by a chain of if statements looks awful, although the design compiler can reduce it. Generally a shift register is the ususal way to generate a serial bitstream. See the code example in another thread related to SPI output.

http://www.alteraforum.com/forum/showthread.php?t=19729

"why I can't compile" is too unspecific to answer, I think.