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Altera_Forum
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16 years ago

New to VHDL. Help with errors

Can you tell me why im getting these errors for this code: LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; ENTITY DAC2 IS PORT( hardwarecontrol: IN STD_LOG...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

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Does this matter?

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Yes. It's against the law (respectively VHDL syntax rules). It seems like you didn't understand the concept of VHDL processes. I suggest a VHDL text book.