New to Quartus, VHDL to Gates?

The number of bits in each Carry/Propagate group is a function of how many inputs the and/or blocks can have and the width of the operands. However in this case, it may be unlimited. Then it looks like the other adders use trees that or the operands, then if a carry is generated in the least significant bit and all other positions or'd are 1there will be a carry out of the most significant. Then if the any position generates a carry and all the bits or'd to any higher position the carry is propagated to that position. Consider 32 bit operands. One carry condition would need 30 inputs to or the propagates between the most and least significant, the and that with the least significant carry, then a 30 input or to or all of the remaining positions(30?), then 29, 28 ... and so on.

Binary integer multiply is a series of add and shifts. If the LSB of the multiplier is 1, add the multiplicand to the product, if 0, do not add, shift the product and multiplier right 1 position, discarding LSB of the multiplier, repeat for the width of the multiplier to produce the product width equal to the sum of m'plier and m'cand widths.

Division essentially does the reverse, but first complement opnds to make both positive and remember if one was negative and the other positive. Trial subtract the divisor from the high half of the double wide dividend, if negative just shift otherwise add 1 to the quotient, shift quotient and dividend 1 position left, repeat for the width of the divisor. What is left of the dividend is the remainder. Also if the signs were different complement the quotient because the algorithm uses positive operands but the result has to be negative.

I may have forgotten some detail, but if you try a case or two with small numbers the basic notion should come thru.