New to Quartus, VHDL to Gates?

I dont understand the problem with the RTL viewer. if you have in and out ports on the entity, they will be pins, with the internal logic connecting them together.

The basic principle to multplication is addition. you need for an n bit number, you need n-1 adders. the idea is you are summing a load of bit-shifted values.

for 7 (111) x 5 (101) = 35:

        1 1 1  (7)
      x 1 0 1  (5)
-----------------
    1 1 1 0 0  x4
+   0 0 0 0 0  x2 (0 in this case
+   0 0 1 1 1
------------------
  1 0 0 0 1 1       = 32 + 2 + 1

As for division, dont even think about it. The best way to do A/B is to actually do A X 1/B where 1/B is pre calculted in fixed point. Division circuits are huge and generally best avoided. Most FPGAs now have embedded multipliers hence why the Ax 1/B calculation is much easier.