Honored Contributor
Honored ContributorAn in response to your "Redstone" logic - your ALU is going to get very complicated, very quickly. Im guessing the clock slows it down because you're actually adding the clocking circuit into the logic. The thing about clocks is it allows for the development of a pipeline. In the real world, there are actual time delays for a signal to pass through logic. Without a clock, it would be a very slow processor. The clock may increase the latency through the design, but you can push much much more data through it.
As Im guessing there is no actual delay through this redstone system, then asynchronous design is possible. I wouldnt try and run much on an FPGA without a clock.
