New to Quartus, VHDL to Gates?

For your first question: when you have compiled some code go to the RTL viewer: Tools -> netlist viewers -> RTL View. That will show you all the gates in the design. But remember that this will have all boolean algebra reduced to minimal design, following the rules of things like

A and A = A

A and !A =0

A or !A = 1

etc

What you want to use is Modelsim. With this you can simulate anything.

You can simulate code directly, and manipulate it from the code. you could write some code like this in VHDL and simulate it and watch the waveform in modesim:

signal a,b,c,d : std_logic;
begin
  a <= '0', '1' after 10 ns, '0' after 30 ns;
  b <= '1', '0' after 40 ns;
  c <= a and b;
  d <= a nand b;
end architecture;

Now you wont be able to compile this in quartus, but at least you can simulate it.