Forum Discussion
WKuzn
New Contributor
New ContributorNew Quartus versions is reason for timing constraints fails
Hello. I am trying to describe the time constraints on a project with an 8-bit DDR bus. I took the sample document from the wiki and the accompanying documentation provided by Rysc user (https://fp...
KhaiChein_Y_Intel
Regular Contributor
Regular ContributorThis setting specifies the propagation delay from an input or bidirectional pin to logic and embedded cells within the device. Use this advanced option after you compile a project, check the I/O timing, and determine that the timing is unsatisfactory.
You can use this option to fine-tune the I/O timing of your design and meeting tSU and tH requirements.
