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WKuzn's avatar
WKuzn
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7 years ago

New Quartus versions is reason for timing constraints fails

Hello. I am trying to describe the time constraints on a project with an 8-bit DDR bus. I took the sample document from the wiki and the accompanying documentation provided by Rysc user (https://fp...
WKuzn's avatar
WKuzn
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7 years ago

Yes, i compiled project with "Auto device Selected by Fitter", Select only Cyclone IV E Family, and -7 speedgrade. After your post, i tried manually select and recompile for EP4CE6E22C6, EP4CE115F29I7, 5CEFA9U19I7 with same timing fails (+-300ps).