Forum Discussion
Altera_Forum
Honored Contributor
15 years agoHi cprodrigues,
Probably this happens because you are using the input clock for the synchronizer and then you sample/latch its output with the pll output clk. You should use the pll clock for the synchronizer, too. I'm not an expert on this point, but I think that you should use pll in source synchronous mode in order to use both clocks and keep under control their relative phase. Cris