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Altera_Forum
Honored Contributor
15 years agoHi Cris
Thanks for your help. It´s a hold slack. My sdc file contains create_clock, derive_pll_clocks, set_clock_uncertainty and derive_clock_uncertainty, as follows: create_clock -name {CLK} -period 20.000 -waveform { 0.000 10.000 } [get_ports {CLK}] derive_pll_clocks -use_tan_name set_clock_uncertainty -rise_from [get_clocks {altpll0:inst1|altpll:altpll_component|altpll_bo32:auto_generated|clk[0]}] -rise_to [get_clocks {altpll0:inst1|altpll:altpll_component|altpll_bo32:auto_generated|clk[0]}] 0.300 derive_clock_uncertainty I'm following tips from timing advisor (at least as I've understood them :) ) Do you see how can I fix this slack?