Need to write timing constraints for PLL generated clocks?

"CLK_48MHz" is the name in my HDL code. Indeed, the 48MHz clock is independent from all others, but also each 25 MHz clock is independent from the other. It is a bit uncommon, but we will use several 25 MHz (programmable) oscillator on the same board to simulate several boards with several oscillator. Do I have to define (slightly) different period for each 25 MHz clock?

My SDC file contains:

create_clock -period 20.833 -name {CLK_48MHz} [get_ports {CLK_48MHz}]

create_clock -period 40.00 -name {CLK_25MHz[0]} [get_ports {CLK_25MHz[0]}]

create_clock -period 40.00 -name {CLK_25MHz[1]} [get_ports {CLK_25MHz[1]}]

create_clock -period 40.00 -name {CLK_25MHz[2]} [get_ports {CLK_25MHz[2]}]

create_clock -period 40.00 -name {CLK_25MHz[3]} [get_ports {CLK_25MHz[3]}]

derive_pll_clocks

set_clock_groups -asynchronous -group {CLK_48MHz } \ ...

...and then I have problems