Need to write timing constraints for PLL generated clocks?

Dear all,

It worked well (at least in Quartus, the board is not designed yet). Then I added one external 48 MHz clock that is not related to the others, and I could write the constraint

set_clock_groups -asynchronous -group {CLK_48MHz }

-group {UclocksLVDS|clocklvds_25_100mhz_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk UclocksLVDS|clocklvds_25_100mhz_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}

It worked well. But now I have five external clocks and four PLLs, and I do not manage to correctly write the SDC file.

My source file contains:

LesPLLs25MHz : for i in CLK_25MHz'range generate

UclocksLVDS : component clockLVDS_25_100MHz

port map (

refclk => CLK_25MHz(i),

rst => RESET, -- '0',

outclk_0 => clk_coeur(i),

outclk_1 => clk_x4(i),

outclk_2 => open, -- clk_x2(i),

locked => pll_lock(i)

);

end generate;

[/INDENT]

And I have tried to write:

set_clock_groups -asynchronous -group {CLK_48MHz }

-group { \LesPLLs25MHz:0:UclocksLVDS|clocklvds_25_100mhz_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk

\LesPLLs25MHz:0:UclocksLVDS|clocklvds_25_100mhz_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk }

-group { \LesPLLs25MHz:1:UclocksLVDS|clocklvds_25_100mhz_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk

\LesPLLs25MHz:1:UclocksLVDS|clocklvds_25_100mhz_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk }

-group { \LesPLLs25MHz:2:UclocksLVDS|clocklvds_25_100mhz_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk

\LesPLLs25MHz:2:UclocksLVDS|clocklvds_25_100mhz_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk } \

-group { \LesPLLs25MHz:3:UclocksLVDS|clocklvds_25_100mhz_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk

\LesPLLs25MHz:3:UclocksLVDS|clocklvds_25_100mhz_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk }

But it is wrong: "Ignored filter at my_filename.sdc(13): ... could not be matched with a clock"

Sometimes I also get <<invalid command name "-group">>

Is it bad to use a vector/generate with clocks?

I did not manage to use the signal names I choose in my source file ("clk_x4", ...).

I could start a new thread...

Thank you in advance