Need help with my .vwf file to simulate my vhdl design file

I'm having an awful time getting my vwf file to simulate correctly. I just keep running into errors. Can someone help me out or point me in the right direction on how to set this up. I understand there are many ways to simulate this but all I want is to add and subtract numbers. I would like to increment AI by 1 and BI by two so their not the same. I'm wanting the simulation to switch operations "addition and subtraction" when my selector "SE" is 1 or 0 like i instructed in my code.

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity add_sub_2 is

port (

AI,BI : in integer range 0 to 15;

SE : in std_logic_vector (2 downto 0);

SO : out integer range 0 to 32);

end add_sub_2 ;

architecture add_sub of add_sub_2 is

BEGIN

WITH SE SELECT

SO <= AI + BI WHEN "000",

AI - BI WHEN "001",

AI + BI WHEN others;

end add_sub ;