Honored ContributorHi.
I need help in such situation: I have Transceiver Module. I want to connect 2 such modules and to simulate their work in ModelSim using testbench. Does anybody have ideas how to perfrom that?
Honored ContributorStart by writing the testbench in VHDL or Verilog.
Honored ContributorI already have testbench for transciever in VHDL. I think only way is to create in Quartus project where 2 transcievers are connected and to write testbench for it. But I'm not shure and want to know maybe there is any easier way.
Honored ContributorYou are right, connect Tx to Rx (loopback). Testbench to send word stimulus for Tx (vector of limited length, repeated). Tx serialises it and is connected directly to Rx. Testbench to check it receives the correct data at Rx from Tx side.
Honored ContributorI have found another way - to declare in test bench 2 instances of TxRxModule and connect them by using PORT MAP.
Comparing with methods that were proposed by myself and kaz, this method gives ability to simulate not ideal module, but to take in account some CLKs missmatch (in real life CLKs frequencies never will be exact the same), time delays and other.
