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Honored Contributor
Honored ContributorNeed help to provide timing constraint and understood the working of Timequest
Hello, I have used two clocks in my design.Both clocks are generated from same PLL.Clock frequency of one clock is 50MHz and frequency of other is 55MHz.I am transferring data between 50MHz and...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- 50 MHz and 55MHz though related can't be synchronous for timing purpose. The tool may compute worse pattern. So you need CDC (using fifo is safe). You can provide false path if you have double synchroniser and taken care of data transfer --- Quote End --- There is a danger when using false paths across domains like this that, in theory, the fitter could place the CDC registers on opposite sides of the chip, which would be a problem. Often it is better to use a max delay instead of a false path. Something that should make it easy for the tool to route but not do something stupid.
