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Altera_Forum
Honored Contributor
10 years agoneed help syntax with sdc
hi, i get a problem working with sdc, i think it's only a syntax one. my top is :
u1 : enet_rx_clk_pllport map(
inclk0 => enet_rx_clk,
c0 => enet_rx_clk_270deg,--...
Altera_Forum
Honored Contributor
10 years agoHi,
usually you don't need constrain the generated clocks if you use "derive_pll_clocks". To get the proper syntax I'm using Timequest. Just start Timequest and create the timing netlist. Then type at TCL console "derive_pll_clocks". Now you will see the correct commands. Jens