Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Need comments on Single port RAM

I am doing a design of Single port ram in VHDL. I need inputs if there are rooms for improvement. Thanks! ---------------------------------------------------------------------------------------...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Due to assigning data_io in a clock sensitive process, you add another clock cycle delay and require a read access duration of two cycles, which is most likely unwanted.

P.S.: I see kaz, already mentioned this.