Need comments on Single port RAM

Hi,

I mean apply Z in a combinatorial assignment, not on the clk edge due to clk latency issues.

Imagine at a clk edge your wr = '1' so your module reads in data_io:

--- Quote Start ---

if (we='1') then

my_ram256x8(conv_integer(address))<=data_io;

end if;

--- Quote End ---

At the same clk edge when wr = '1' you apply Z on data_io, fair enough

but this means data_io will become Z(will be cutoff) just after this edge.

so when you take data_io to your ram it is still not cutoff from your own drive.

--- Quote Start ---

if rising_edge (clk) then

if (oe = '1' and we = '0') then

data_io <= data_out;

else

data_io <= "ZZZZZZZZ";

end if;

end if;

end process;

--- Quote End ---

Here is my version(off my head so check for mistakes):

entity ram1 is

port(

clk : in std_logic;

we : in std_logic;

oe : in std_logic;

address: in std_logic_vector(7 downto 0);

data_io : inout std_logic_vector(7 downto 0)

);

end ram1;

architecture rtl of ram1 is

signal data_out : std_logic_vector(7 downto 0);

type ram_type is array (255 downto 0) of std_logic_vector(7 downto 0);

signal my_ram256x8 : ram_type := (others => (others => '0'));

begin

data_io <= data_out when (oe = '1' and we = '0') else (others => 'Z');

process(clk)

begin

if rising_edge(clk) then

if oe = '1' then

if we = '1' then

my_ram(conv_integer(address)) <= data_io; -- write

else

data_out <= my_ram(conv_integer(address)); -- read

end if;

end if;

end if;

end process;

end rtl;