Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Need comments on Single port RAM

I am doing a design of Single port ram in VHDL. I need inputs if there are rooms for improvement. Thanks! ---------------------------------------------------------------------------------------...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Hi,

comment 1:

why use bidirectional data. If you are inside the fpga you got plenty of noodles to connect. bidir is meant for pins

comment 2:

be careful about bus contention in relation to clocks. My gut feeling you are driving data_io while reading it in...you better use comb for Z assignment