Need comments on Single port RAM

Thanks for pointing out the mistake. It was a mistake there. Sorry! Using automatic generation of code would not do any good for learning process.

Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ram1 is
	PORT(address: 	in std_logic_vector(7 downto 0);
			 clk: 	in std_logic;
	          we: 	in std_logic;
	          oe:   in std_logic;
	     data_io:	inout std_logic_vector(7 downto 0));
end ram1;
ARCHITECTURE rtl OF ram1 IS
    signal data_out : std_logic_vector(7 downto 0);
	TYPE ram_type IS ARRAY(255 downto 0) OF std_logic_vector(7 DOWNTO 0);
	SIGNAL my_ram256x8 : ram_type:=(others=>(others=>'0'));
BEGIN
process (clk)
begin
if rising_edge (clk) then
	if (oe = '1' and we = '0') then
		data_io <= data_out;
    else
        data_io <= "ZZZZZZZZ";
    end if;
    end if;
end process;
	
process(clk)
begin
if (clk'event and clk='1') then
	if (we='1') then
		my_ram256x8(conv_integer(address))<=data_io;
	end if;
end if;
end process;
	
process(clk)
begin
if (clk'event and clk='1') then
	if (we='0' and oe='1') then
		data_out<=my_ram256x8(conv_integer(address));
	end if;
end if;
end process;
END rtl;