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Altera_Forum
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8 years ago

NDRnage Kernels Global Memory Write Pattern

I came up with some basic questions, which I would like to discuss: 1) I still don't understand how SIMD is being implemented in FPGA. In GPU, workitems being assigned to SIMDs are being execut...
Altera_Forum's avatar
Altera_Forum
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8 years ago

Thanks much sstrell,

Here some more questions I have:

1) If the value of number of SIMD, really duplicates the pipelines in the compute units, then there should be a significant difference in resource usage between SIMD 8 and SIMD16. Looking at the resource usage, it tells me increasing SIMD value does not necessarily increases the amount of resource usage. Does it mean SIMD pipeline replication is efficient in terms of area growth?

3) Can you elaborate more on this? Isn't barrier introduces severe performance penalty though?

4) So you are telling there is no runtime mechanism for memory coalescing, and it's all compile time. Is that true? Cause I think for GPU is the other way.