Forum Discussion
Altera_Forum
Honored Contributor
12 years agoIt seems the important message is:
Info: NativeLink has detected a mixed Verilog and VHDL design -- none simulation models will be used A report of a simulation I done is: Info: NativeLink has detected VHDL design -- vhdl simulation models will be used Some reports on the Web, show mixed Verilog and VHDL design, but says "vhdl simulation models will be used" instead. Did you use vhdl and verilog codes?