my scheme simulation is ok , but test have errors

Hi,

These errors mean there are errors in your verilog/VHDL code.

Error: (vlog-13069) Waveform.vwf.vt(40): near "1": syntax error, unexpected INTEGER NUMBER, expecting IDENTIFIER or TYPE_IDENTIFIER or NETTYPE_IDENTIFIER.

From the bdf I can see that your output signal names start with a number. This isn't allowed in verilog/VHDL and you need to rename them starting with an alphabet.

Error: (vlog-13069) Waveform.vwf.vt(50): near "Q0": syntax errir, unexpected IDENTIFIER, expecting ')'.

I can't tell why you get this error from your bdf. Can you attach the "Waveform.vwf.vt" file?

Regards,

Nurina