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Altera_Forum
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14 years ago

Mux INOUT port in VHDL

Hi all! Currently I'm trying to connect my I2C master module to one of four I2C slaves using a mux without success: I can't get the bidirectional SDA signal to correctly mux. The code is as foll...
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Altera_Forum
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14 years ago

Hi FvM!

Many thanks for checking. What can I do to allow you to verify my problem? If I try to synthesise my project, Quartus complains

Error: Illegal directional connection from the pin "O3_DDCSDA" to the node "EDIDOutput:EDIDOutput|Mux0"

Error: Illegal directional connection from the pin "O2_DDCSDA" to the node "EDIDOutput:EDIDOutput|Mux0"

Error: Illegal directional connection from the pin "O1_DDCSDA" to the node "EDIDOutput:EDIDOutput|Mux0"

Error: Illegal directional connection from the pin "O4_DDCSDA" to the node "EDIDOutput:EDIDOutput|Mux0"

where O?_DDCSDA are the members of the sda vector and EDIDOutput is the module my mux code is in. If I double click on any of the messages Quartus highlights the line "i_sda_i <= to_x01(sda(sel));".

Best regards

Pauliman