Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Mux - Verilog code question

Hello everyone. Mux verilog code below. They do the same, but option 2 got huge delays and cannot meet timing. Conclusion: they have different fitter results but I thought they are the sam...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

thanks fvm,

your code example is a nice idea and I guess what you say is correct.

I will try it later when I have time.

But I'm still wondering, In my code I'm using all cases, TxWrnum is 4 bits and all the 16 cases are defined, I think the problem is on the RHS that actually is much more complex than the example I gave.

I will check later.

thanks