Multiplication VHDL

wow, many problems.

1. Std_logic_vector cannot have -ve indeces.

2. Even with correct indeces lengths, CD(0) would have 16 bits, not 4, so CD(i) <= code(15 downto 12); would have an error from incorrect sizes.

2. Sum and temp are integers, hence you cannot index to individual bits.

3. data(i) is a single std_logic. You cannot do std_logic * std_logic_vector. Hence, there is no possible result, and to_integer is not appropriate.

4. i <= i + 1; is illegal as i is a constant, not a signal.

5. you cannot cast in integer to a std_logic_vector directly, you need to go via the signed or unsigned type.

Q <= std_logic_vector( to_unsigned(AB, Q'length));

I highly suggest you go back to your VHDL manual and start reading it.