Multiplication VHDL

Hi !

plz can you help me to correct :

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity correla is

port (

clk : in std_logic ;

rst : in std_logic ;

data: in std_logic_vector(11 downto 0) ;

code: in std_logic_vector(15 downto 0 ) ;

Q :out std_logic_vector(17 downto 0) ) ;

end entity ;

architecture arch of correla is

type RAM is array (0 to 3) of std_logic_vector(-8 to 7) ;

signal CD : RAM;

signal temp :integer range 0 to 15;

signal idata :std_logic_vector(11 downto 0) ;

signal sum :integer range 0 to 16 ;

signal AB :integer range 0 to 17 ;

begin

F:for j in 0 to 3 generate

CD(j)<=to_integer(signed(code((4*j+3) downto (4*j))));

end generate F ;

étalement:process(clk,rst)

begin

if(rst='1') then

Q <=(others=>'0');

temp<=0;

AB <=0;

else

if(clk'event and clk ='1') then

sum<=0;

for i in 0 to 3 loop

temp(i)<=to_integer(data(i)*CD(i)) ;

i<= i+1 ;

sum(i)<=sum(i) +temp(i) ;

if(i=3) then

idata<=data;

end if;

end loop ;

AB<=sum ;

Q<=std_logic_vector(AB) ;

end if ;

end if ;

end process ;

end architecture ;

erreur : Error (10511): VHDL Qualified Expression error at correla.vhd(29): TO_INTEGER type specified in Qualified Expression must match std_logic_vector type that is implied for expression by context

Thanks a lot