Multiplication VHDL

Hi,

I am not sure but you should remove the line "use IEEE.std_logic_arith.all;", It may redefine operators.

Avoid éèçàù... : c'est trop français pour du VHDL ;-)

Be aware that integer = 32 bits in VHDL

VHDL needs a very strict description :

Your 'i' is integer range 0 to 3. OK

somewhere you have

i<=i+1 ;

What happens if i = 3 ? Not sure that i returns to 0 !

if i <= 3 then
   i <= i + 1;
else
   i <= 0;
end if;

What is the value of "sum" when rst = '1' ?

You must initialize ALL signals to avoid spending hours to debug.

...

...

BUT your VHDL does NOT describe your schéma !!!

For a beginner, If your design have always 4 mult and 3 add,

I advise you to draw your schema completely : all signals are named.

Write your VHDL element per element :

mult1 : ... <= ... * ... ;

mult2 : ... <= ... * ...;

...

add1 : ... <= ... + ....; -- be careful that with IEEE.numeric_std : 16bits + 16bits => 16bits, not 17bits !!

And add a D flip flop at the end, to stay synchronous.

To create a D flip flop, it is just a

process(rst,clk)
begin
if rst = '1' then
   Q <= (others => '0');
elsif rising_edge(clk) then
   Q <= AB; -- AB is the result of the "logique combinatoire" which may glitchs
end if;
end process;

later, you can make this design more generic as you badly tried. use generic, generate...

In a near future, if fmax is not satisfied, you can pipeline : insert D flip flop between mult and add, but it increase latency.

Welcome to the dark side of VHDL ;-)

golden rule[/orange] : vhdl is a description language, NOT a program.